Commit ff6738b8 by vielex

Final version of ADC.c

parent ce5af639
Showing with 23 additions and 2 deletions
...@@ -31,7 +31,23 @@ ...@@ -31,7 +31,23 @@
// SS3 1st sample source: channel 1 // SS3 1st sample source: channel 1
// SS3 interrupts: enabled but not promoted to controller // SS3 interrupts: enabled but not promoted to controller
void ADC0_Init(void){ void ADC0_Init(void){
volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000010; // 1) activate clock for Port E
delay = SYSCTL_RCGC2_R; // allow time for clock to stabilize
GPIO_PORTE_DIR_R &= ~0x04; // 2) make PE2 input
GPIO_PORTE_AFSEL_R |= 0x04; // 3) enable alternate function on PE2
GPIO_PORTE_DEN_R &= ~0x04; // 4) disable digital I/O on PE2
GPIO_PORTE_AMSEL_R |= 0x04; // 5) enable analog function on PE2
SYSCTL_RCGC0_R |= 0x00010000; // 6) activate ADC0
delay = SYSCTL_RCGC2_R;
SYSCTL_RCGC0_R &= ~0x00000300; // 7) configure for 125K
ADC0_SSPRI_R = 0x0123; // 8) Sequencer 3 is highest priority
ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3
ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger
ADC0_SSMUX3_R &= ~0x000F; // 11) clear SS3 field
ADC0_SSMUX3_R += 1; // set channel Ain1 (PE2)
ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0
ADC0_ACTSS_R |= 0x0008; // 13) enable sample sequencer 3
} }
...@@ -40,5 +56,10 @@ void ADC0_Init(void){ ...@@ -40,5 +56,10 @@ void ADC0_Init(void){
// Input: none // Input: none
// Output: 12-bit result of ADC conversion // Output: 12-bit result of ADC conversion
unsigned long ADC0_In(void){ unsigned long ADC0_In(void){
return 0; // replace this line with proper code unsigned long result;
ADC0_PSSI_R = 0x0008; // 1) initiate SS3
while((ADC0_RIS_R&0x08)==0){}; // 2) wait for conversion done
result = ADC0_SSFIFO3_R&0xFFF; // 3) read result
ADC0_ISC_R = 0x0008; // 4) acknowledge completion
return result;
} }
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